Praha-Vinoř, Czech Republic
Praha-Vinoř, Czech Republic
Keynotes
Electronic Design Automation for Resistive RAM-Based Digital Computing-in-Memory
Speaker: Chandan Kumar Jha (AGRA, University of Bremen, Germany)
Electronic Design Automation (EDA) has enabled the development of modern chips containing billions of transistors. Similar methodologies are therefore essential to make digital computing using emerging technologies practical and scalable. To accelerate the feasibility of such technologies, parallel research efforts are being undertaken worldwide. While some methodologies are being developed from scratch, others are adapted and tailored from existing technologies.
This talk focuses on recent developments in the use of Resistive Random Access Memory (RRAM) for digital Computing-in-Memory (CiM). Following a bottom-up approach, the talk explores multiple levels of the computing stack that contribute to the feasibility of RRAM-based CiM systems.
First, the talk discusses RRAM devices and the properties that make them suitable for digital computing. Second, it presents methods for mapping arbitrary designs onto RRAM crossbar architectures. Third, it introduces automated techniques for generating netlists corresponding to these mappings on RRAM crossbars. Finally, the talk covers automated formal verification strategies employed to ensure the correctness of the transformation process during both synthesis and netlist generation stages.
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Chandan Kumar Jha received his B.Tech. degree from the National Institute of Technology Meghalaya, India, in 2015, and his Ph.D. in Electrical Engineering from the Indian Institute of Technology Gandhinagar, India, in 2020. During his academic career, he received several prestigious awards, including the Merit scholarship during his B.Tech., the Visvesvaraya Fellowship, and the Intel India Fellowship during his Ph.D. He has held postdoctoral research positions at the Indian Institute of Technology Bombay, India, and at the German Research Center for Artificial Intelligence (DFKI), Germany. He is currently a Postdoctoral Researcher at the University of Bremen, Germany, in the Computer Architecture group led by Prof. Rolf Drechsler. He serves as an Associate Editor for the ACM Transactions on Design Automation of Electronic Systems (TODAES) and has been a member of the Technical Program Committee (TPC) for several premier conferences in design automation and computing systems. |
Industrial talks
Tapeout Is Not the End: Creative Ways to Fix Silicon Surprises
Speaker: Jakub Šťastný (ASICentrum, Praha)
Manufacturing of an integrated circuit is an expensive process and if we find a bug in the prototypes during the validation and qualification, the respin can be costly. Even in case of a perfect circuit we still might need to change the device because of the process variations or a need to adapt to the changing specification. Several approaches exist to minimize the cost of the IC change. We will describe the main ones in the presentation, show their advantages and disadvantages, and discuss the risks and challenges. In the second part of the presentation we will present some case studies of bugfixes – from the most trivial fix to the complex one.
| Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple sensor chips to SoC systems. |
Embedded Systems Development in Mid-Sized R&D: From Specification to Mass Production
Speaker: Tomáš Dresler (2N TELEKOMUNIKACE a.s.)
This lecture provides a pragmatic, inside look into the complete product lifecycle within a modern mid-sized engineering company. Moving away from academic stereotypes of isolated low-level programming, we present the "end-to-end" journey of two real-world projects through the lens of modern software engineering applied to hardware platforms.
The presentation outlines the dynamics of an agile R&D department where a team of 6.5 embedded developers works under the guidance of a technical architect and closely cooperates with 2 dedicated QA testers. We focus heavily on modern software craftsmanship in the embedded domain, demonstrating how clean code principles such as KISS (Keep It Simple, Stupid) and DRY (Don't Repeat Yourself) are strictly enforced during architecture design and peer reviews. Attendees will explore a state-of-the-art workflow utilizing GitLab CI/CD for automated static analysis, Dockerized builds, and automated deployment to physical test-racks. Furthermore, the lecture covers the crucial phases where software meets hardware—specifically during initial prototype bring-up, hardware-interface debugging using logic analyzers, and the creation of automated production test protocols (jigs).
The goal is to motivate graduate engineering students by demonstrating that contemporary embedded development is a sophisticated branch of software architecture that combines strict software disciplines with the tangible satisfaction of shipping high-volume physical products to global markets.
Keywords: Embedded Software, Software Architecture, GitLab CI/CD, KISS/DRY, Hardware Bring-up, Product Lifecycle.
Keynotes
Electronic Design Automation for Resistive RAM-Based Digital Computing-in-Memory
Speaker: Chandan Kumar Jha (AGRA, University of Bremen, Germany)
Electronic Design Automation (EDA) has enabled the development of modern chips containing billions of transistors. Similar methodologies are therefore essential to make digital computing using emerging technologies practical and scalable. To accelerate the feasibility of such technologies, parallel research efforts are being undertaken worldwide. While some methodologies are being developed from scratch, others are adapted and tailored from existing technologies.
This talk focuses on recent developments in the use of Resistive Random Access Memory (RRAM) for digital Computing-in-Memory (CiM). Following a bottom-up approach, the talk explores multiple levels of the computing stack that contribute to the feasibility of RRAM-based CiM systems.
First, the talk discusses RRAM devices and the properties that make them suitable for digital computing. Second, it presents methods for mapping arbitrary designs onto RRAM crossbar architectures. Third, it introduces automated techniques for generating netlists corresponding to these mappings on RRAM crossbars. Finally, the talk covers automated formal verification strategies employed to ensure the correctness of the transformation process during both synthesis and netlist generation stages.
|
Chandan Kumar Jha received his B.Tech. degree from the National Institute of Technology Meghalaya, India, in 2015, and his Ph.D. in Electrical Engineering from the Indian Institute of Technology Gandhinagar, India, in 2020. During his academic career, he received several prestigious awards, including the Merit scholarship during his B.Tech., the Visvesvaraya Fellowship, and the Intel India Fellowship during his Ph.D. He has held postdoctoral research positions at the Indian Institute of Technology Bombay, India, and at the German Research Center for Artificial Intelligence (DFKI), Germany. He is currently a Postdoctoral Researcher at the University of Bremen, Germany, in the Computer Architecture group led by Prof. Rolf Drechsler. He serves as an Associate Editor for the ACM Transactions on Design Automation of Electronic Systems (TODAES) and has been a member of the Technical Program Committee (TPC) for several premier conferences in design automation and computing systems. |
Industrial talks
Tapeout Is Not the End: Creative Ways to Fix Silicon Surprises
Speaker: Jakub Šťastný (ASICentrum, Praha)
Manufacturing of an integrated circuit is an expensive process and if we find a bug in the prototypes during the validation and qualification, the respin can be costly. Even in case of a perfect circuit we still might need to change the device because of the process variations or a need to adapt to the changing specification. Several approaches exist to minimize the cost of the IC change. We will describe the main ones in the presentation, show their advantages and disadvantages, and discuss the risks and challenges. In the second part of the presentation we will present some case studies of bugfixes – from the most trivial fix to the complex one.
| Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple sensor chips to SoC systems. |
Embedded Systems Development in Mid-Sized R&D: From Specification to Mass Production
Speaker: Tomáš Dresler (2N TELEKOMUNIKACE a.s.)
This lecture provides a pragmatic, inside look into the complete product lifecycle within a modern mid-sized engineering company. Moving away from academic stereotypes of isolated low-level programming, we present the "end-to-end" journey of two real-world projects through the lens of modern software engineering applied to hardware platforms.
The presentation outlines the dynamics of an agile R&D department where a team of 6.5 embedded developers works under the guidance of a technical architect and closely cooperates with 2 dedicated QA testers. We focus heavily on modern software craftsmanship in the embedded domain, demonstrating how clean code principles such as KISS (Keep It Simple, Stupid) and DRY (Don't Repeat Yourself) are strictly enforced during architecture design and peer reviews. Attendees will explore a state-of-the-art workflow utilizing GitLab CI/CD for automated static analysis, Dockerized builds, and automated deployment to physical test-racks. Furthermore, the lecture covers the crucial phases where software meets hardware—specifically during initial prototype bring-up, hardware-interface debugging using logic analyzers, and the creation of automated production test protocols (jigs).
The goal is to motivate graduate engineering students by demonstrating that contemporary embedded development is a sophisticated branch of software architecture that combines strict software disciplines with the tangible satisfaction of shipping high-volume physical products to global markets.
Keywords: Embedded Software, Software Architecture, GitLab CI/CD, KISS/DRY, Hardware Bring-up, Product Lifecycle.