Quality, Reliability, and Security: Intertwined Challenges in Dependable Computing Systems

Speaker: Marco Ottavi (University of Rome Tor Vergata, Italy; University of Twente, Netherlands)

Modern computing systems must operate correctly despite manufacturing defects, mission-time faults, environmental stress, and malicious attacks. This keynote discusses the intertwined nature of quality, reliability, and security in dependable computing systems, showing why these dimensions can no longer be treated independently.
Starting from manufacturing test and design-for-testability, the talk will connect defect coverage and test escapes to mission-time reliability, fault mechanisms, radiation effects, and redundancy schemes. It will then extend the discussion to hardware trust and vulnerability, including hardware Trojans, side-channel attacks, fault injection, and security primitives such as PUFs and TRNGs.
The central message is that dependable systems require integrated design and validation methodologies across the full lifecycle, from production to deployment, where random faults and malicious threats are addressed within a common framework.

Marco Ottavi, Ph.D.

Marco Ottavi is Associate Professor in Electronic Engineering at the University of Rome Tor Vergata and Associate Professor at the University of Twente. His research and teaching are centered on dependable computing systems, with a particular focus on the design, test, validation, reliability, and security of computing architectures for critical and high-reliability applications. His work addresses one of the central challenges of modern computing: ensuring that systems continue to operate correctly in the presence of manufacturing defects, mission-time faults, environmental stress, radiation effects, and malicious attacks. His research spans design-for-testability, fault tolerance, redundancy techniques, radiation effects in digital systems, fault injection, hardware Trojans, side-channel vulnerabilities, security primitives, and secure and reliable RISC-V architectures. A distinctive aspect of his work is the integration of quality, reliability, and security into a unified view of system dependability. This perspective reflects the growing need for computing systems that are not only functionally correct, but also resilient, trustworthy, and robust throughout their lifecycle, from production test to deployment in demanding operational environments. Before his current academic appointments, he worked as a Senior Design Engineer at Advanced Micro Devices and held postdoctoral research positions at Sandia National Laboratories and Northeastern University. He has authored numerous publications in international journals and conferences and actively contributes to the scientific community through editorial, reviewing, and conference organization roles.

Electronic Design Automation for Resistive RAM-Based Digital Computing-in-Memory

Speaker: Chandan Kumar Jha (AGRA, University of Bremen, Germany)

Electronic Design Automation (EDA) has enabled the development of modern chips containing billions of transistors. Similar methodologies are therefore essential to make digital computing using emerging technologies practical and scalable. To accelerate the feasibility of such technologies, parallel research efforts are being undertaken worldwide. While some methodologies are being developed from scratch, others are adapted and tailored from existing technologies.
This talk focuses on recent developments in the use of Resistive Random Access Memory (RRAM) for digital Computing-in-Memory (CiM). Following a bottom-up approach, the talk explores multiple levels of the computing stack that contribute to the feasibility of RRAM-based CiM systems.
First, the talk discusses RRAM devices and the properties that make them suitable for digital computing. Second, it presents methods for mapping arbitrary designs onto RRAM crossbar architectures. Third, it introduces automated techniques for generating netlists corresponding to these mappings on RRAM crossbars. Finally, the talk covers automated formal verification strategies employed to ensure the correctness of the transformation process during both synthesis and netlist generation stages.

Chandan Kumar Jha, Ph.D.

Chandan Kumar Jha received his B.Tech. degree from the National Institute of Technology Meghalaya, India, in 2015, and his Ph.D. in Electrical Engineering from the Indian Institute of Technology Gandhinagar, India, in 2020. During his academic career, he received several prestigious awards, including the Merit scholarship during his B.Tech., the Visvesvaraya Fellowship, and the Intel India Fellowship during his Ph.D. He has held postdoctoral research positions at the Indian Institute of Technology Bombay, India, and at the German Research Center for Artificial Intelligence (DFKI), Germany. He is currently a Postdoctoral Researcher at the University of Bremen, Germany, in the Computer Architecture group led by Prof. Rolf Drechsler. He serves as an Associate Editor for the ACM Transactions on Design Automation of Electronic Systems (TODAES) and has been a member of the Technical Program Committee (TPC) for several premier conferences in design automation and computing systems.

Building Radiation-Tolerant Detector Systems: From Sensors to Qualification

Speaker: Petr Gallus (UJP Praha)

Developing detector systems for radiation environments requires much more than designing a sensor. Reliable operation in medical, nuclear, and space applications demands the integration of detectors, custom microelectronics, readout electronics, data processing, and radiation qualification into a single development process.
This presentation introduces detector technologies developed at UJP PRAHA, including hybrid pixel detectors, custom ASICs, FPGA-based readout systems, and irradiation facilities used for radiation hardness evaluation. Several case studies will illustrate how detector concepts are transformed into qualified systems deployed in real-world applications.
The talk highlights key engineering challenges, lessons learned, and future directions in the development of radiation-tolerant detector systems.

Tapeout Is Not the End: Creative Ways to Fix Silicon Surprises

Speaker: Jakub Šťastný (ASICentrum, Praha)

Manufacturing of an integrated circuit is an expensive process and if we find a bug in the prototypes during the validation and qualification, the respin can be costly. Even in case of a perfect circuit we still might need to change the device because of the process variations or a need to adapt to the changing specification. Several approaches exist to minimize the cost of the IC change. We will describe the main ones in the presentation, show their advantages and disadvantages, and discuss the risks and challenges. In the second part of the presentation we will present some case studies of bugfixes – from the most trivial fix to the complex one.

AI Inference Optimization for Resource Constrained Edge Devices

Speaker: Pavel Macenauer (NXP Semiconductors)

Optimizing neural networks is key to their deployment on embedded and mobile devices - from driver‑assistance systems in cars to health‑tracking features on your smart watch. We will analyze challenges of deploying AI on resource‑constrained hardware, explore use cases such as face recognition, voice assistants, or industrial anomaly detection, and dive into algorithms that make this possible without a connection to the cloud.

Pavel Macenauer

Pavel Macenauer is an R&D director at NXP Semiconductors, where he oversees the development of neural network tooling and runtime software which enable state-of-the-art AI technologies on NXP hardware, up-streams to frameworks such as PyTorch and with his teams contributes to other widely used opensource projects. Before joining NXP, he worked in image processing, computer vision, and large‑scale data analysis in the aerospace and imaging sectors. He holds degrees from the Faculty of Electrical Engineering at the Czech Technical University in Prague and the Faculty of Information Technology at Brno University of Technology.

Embedded Systems Development in Mid-Sized R&D: From Specification to Mass Production

Speaker: Tomáš Dresler (2N TELEKOMUNIKACE a.s.)

This lecture provides a pragmatic, inside look into the complete product lifecycle within a modern mid-sized engineering company. Moving away from academic stereotypes of isolated low-level programming, we present the "end-to-end" journey of two real-world projects through the lens of modern software engineering applied to hardware platforms. The presentation outlines the dynamics of an agile R&D department where a team of 6.5 embedded developers works under the guidance of a technical architect and closely cooperates with 2 dedicated QA testers. We focus heavily on modern software craftsmanship in the embedded domain, demonstrating how clean code principles such as KISS (Keep It Simple, Stupid) and DRY (Don't Repeat Yourself) are strictly enforced during architecture design and peer reviews. Attendees will explore a state-of-the-art workflow utilizing GitLab CI/CD for automated static analysis, Dockerized builds, and automated deployment to physical test-racks. Furthermore, the lecture covers the crucial phases where software meets hardware—specifically during initial prototype bring-up, hardware-interface debugging using logic analyzers, and the creation of automated production test protocols (jigs). The goal is to motivate graduate engineering students by demonstrating that contemporary embedded development is a sophisticated branch of software architecture that combines strict software disciplines with the tangible satisfaction of shipping high-volume physical products to global markets. Keywords: Embedded Software, Software Architecture, GitLab CI/CD, KISS/DRY, Hardware Bring-up, Product Lifecycle.

Coordinated Vulnerability Disclosure in Auditable Silicon: Balancing Openness and Need-to-Know, First Experience

Speaker: Stanislav Jeřábek (Tropic Square)

The lifecycle security of a product is an important part of overall security, since security is an infinite game and product launch is just the beginning. Upcoming EU legislation in the form of the Cyber Resilience and Cyber Security Acts (CRA and CSA) emphasizes the product security lifecycle and mandates new obligations. These include continual security assessment, adoption of SBOMs, and running a Coordinated Vulnerability Disclosure (CVD) process.
Tropic Square, as the provider of the first open, auditable secure element, has always emphasized a proactive role in the endless security game. We do this by promoting independent, accessible validation, not hiding design details behind NDAs, and actively collaborating with academic labs.
Recently we experienced our first CVD case due to a vulnerability disclosed by an external laboratory. This case tested our defined CVD scenario and led us to reshape the CVD process, taking it beyond the current industry standard and even future legislative requirements.

Stanislav Jeřábek, Ph.D.

Stanislav Jeřábek is an Assistant Professor at the Faculty of Information Technology, CTU in Prague, and a Security Researcher at Tropic Square s.r.o. His professional and research focus is on side-channel attack (SCA) evaluation, with particular emphasis on the validation of security primitives and the SCA robustness of secure implementations.