PESW 2018
PESW 2018
The 6th Prague Embedded Systems Workshop
June 28-30, 2018
Roztoky u Prahy, Czech Republic
PESW 2018
The 6th Prague Embedded Systems Workshop
June 28-30, 2018
Roztoky u Prahy, Czech Republic

Keynotes

The list of keynotes is not complete yet.

Cross-Layer System-Level Reliability Estimation

Speaker: Alberto Bosio, LIRMM Montpellier, France

Cross-layer approach is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. In other words, the designer has to know what are the “critical” components of the system in order to properly introduce error management mechanisms. Unfortunately, system-level reliability estimation is a complex task that usually requires huge simulation campaign. This presentation aims at proposing a cross-layer system-level reliability analysis framework for soft-errors in microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics.

Experimental results, carried out on different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9), show that the simulation time is significantly lower than state-of-the-art fault-injection experiments with an accuracy high enough to take effective design decision.

Alberto Bosio

Alberto Bosio received the PhD in Computer Engineering from Politecnico di Torino in Italy in 2006 and the HDR (Habilitation Diriger les Recherches) in 2015 from the University of Montpellier (France). Currently he is an associate professor in the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM)-University of Montpellier in France. He has published articles in publications spanning diverse disciplines, including memory testing, fault tolerance, diagnosis and functional verification. He is an IEEE member and the chair of the European Test Technology Technical Council (ETTTC).


Keynotes

The list of keynotes is not complete yet.

Cross-Layer System-Level Reliability Estimation

Speaker: Alberto Bosio, LIRMM Montpellier, France

Cross-layer approach is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. In other words, the designer has to know what are the “critical” components of the system in order to properly introduce error management mechanisms. Unfortunately, system-level reliability estimation is a complex task that usually requires huge simulation campaign. This presentation aims at proposing a cross-layer system-level reliability analysis framework for soft-errors in microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics.

Experimental results, carried out on different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9), show that the simulation time is significantly lower than state-of-the-art fault-injection experiments with an accuracy high enough to take effective design decision.

Alberto Bosio

Alberto Bosio received the PhD in Computer Engineering from Politecnico di Torino in Italy in 2006 and the HDR (Habilitation Diriger les Recherches) in 2015 from the University of Montpellier (France). Currently he is an associate professor in the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM)-University of Montpellier in France. He has published articles in publications spanning diverse disciplines, including memory testing, fault tolerance, diagnosis and functional verification. He is an IEEE member and the chair of the European Test Technology Technical Council (ETTTC).