Horoměřice, Czech Republic
Horoměřice, Czech Republic
Keynotes
Colorful like a Chameleon: (In)Security of Wireless Access Control Systems
Speakers: Timo Kasper (Ruhr-University, Bochum, Germany; Kasper&Oswald GmbH.) and Tomáš Přeučil (FIT, CTU in Prague)
Wireless embedded devices have become omnipresent in applications such
as access control (to doors or to PCs), identification, and payments.
The talk reviews the security of several commercial devices that
typically employ cryptographic mechanisms as a protection against
ill-intended usage or to prevent unauthorized access. A combination of
side-channel attacks, reverse-engineering and mathematical cryptanalysis
helps to reveal and exploit weaknesses in the systems that for example
allow opening secured doors in seconds. At hand of real-world examples
and live demos, the implications of a key extraction for the security of
the respective contactless application are illustrated. As a powerful
tool for security-analyzing and pentesting NFC and RFID systems, the
open-source project “ChameleonMini” is presented: Besides
virtualization and emulation of contactless cards, the device allows to
log the NFC communication, and in its latest Revision G acts as an
active RFID reader to copy contactless cards on-the-fly.
Dr.-Ing. Timo Kasper is executive director of Kasper&Oswald GmbH (KAOS),
founded in 2012 together with Prof. Dr.-Ing. David Oswald, offering
innovative products and various services for (embedded) security
engineering. Timo has studied electrical engineering and information
technology at the Ruhr-University Bochum, Germany and at the University
of Sheffield, UK. His Diploma thesis (2006) and his PhD thesis (2012)
were awarded with a first prize in IT Security. Timo’s field of
expertise covers the security of embedded cryptographic systems, such as
smartcards, RFID and other (wireless) technology, including penetration
testing and implementation attacks.
Tomáš Přeučil, MSc. is a PhD student at the Faculty of Information Technology (FIT) at the Czech Technical University in Prague. His research focuses on the security of pervasive devices including access control systems and RFID card security, as well as attacks on non-IP-based networks.
Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits?
Speaker: Andreas Steininger (Vienna University of Technology, Austria)
While the synchrony obtained by a global clock simplifies design and implementation of digital circuits considerably, it also constitutes a strong assumption. This becomes perceivable by the clock distribution problems in high-speed circuits, but also by the uncontrolled error behavior that synchronous circuits usually exhibit upon even a small timing violation. Due to their much more flexible and self-regulated timing, asynchronous circuits do not need a sophisticated clock tree and can accommodate timing variations and delay-related faults naturally. In this talk we will survey approaches to complement this important time-domain property though explicit value-domain fault-tolerance provisions on coding- and circuit-level. In addition, we will investigate how the fail-stop property inherent to asynchronous circuits can be leveraged for easy recovery after repair of a permanent fault, and hence forms an interesting foundation for building self-repairing circuits.
Andreas Steininger studied Electrical Engineering at TU Wien where he also finished his PhD thesis in 1994, and is now working as an Associate Professor at the Department of Computer Engineering. He has been involved in many industrial and scientific projects concerned with real-time communication networks, the design of fault-tolerant / radiation-tolerant computer architectures and their evaluation by means of fault-injection, and testing. His current research focuses on asynchronous (“clockless”) logic design, timing-domain interfacing, metastability, and GALS architectures. He has published over 190 papers in journals and at international conferences and is co-inventor of over 10 patents. He has supervised more than 20 successful PhD theses and serves as the Director for the Vienna PhD School of Informatics and as chair of the Doctoral College Resilient Embedded Systems. Three of his master students have been winners of the faculty's highly competitive "Distinguished Young Alumnus Award" for the best diploma thesis.
Digital simulator: from the RTL to the full chip simulations of a low power SoC ASIC
Speaker: Jakub Šťastný (ASICentrum, s.r.o.)
Digital simulator is the basic tool to examine the behavior of the designed digital block. However, digital simulator can support designer's work also beyond the purely digital world - the whole ASIC can be modeled in it on the system level including analog blocks and power supply networks. During the talk we will discuss challenges brought by the full low-power SoC ASIC simulation and present a handful of case studies how we utilized the capabilities of a modern digital simulator.
Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple senzor chips to SoC systems.
Security Issues in Cyber Physical Cognitive Systems
Speaker: Virendra Singh (Indian Institute of Technology Bombay, Mumbai, India)
Migration to Society 5.0 has mandated to go for Industry 5.0 whose priority is to utilize human and machines synergistically. In order to achieve the above stated objective, Cyber Physical Systems (CPS) has become the central part of the Industry 5.0. Industry 5.0 demands cognitive computing along with the Cyber Physical Systems. Industry 5.0 aims at utilizing human and machine synergistically.
On the other hand, with sophisticated cyber attacks all over the world, it is clear that the attackers are well-funded through organized crimes, nation–support, etc. Thus, it has become important to address cyber threat intelligence to prevent some of the ulterior motives of the attackers to use attacks as weapons, in particular, when most of the public infrastructures are driven by sophisticated IT systems and further with the policy of building several smart-cities to address various societal issues. The latter naturally will lead to growth of Internet of Things (IoT), which in turn will increase the attack surface of the underlying infrastructure due to their vulnerabilities, malware susceptibility, and an emergence of denial-of-service (DoS) attacks will be acutely felt. Therefore the system must aims at the infrastructures with proactive sensing of cyber-physical systems using data from physical sensors and integrated from other relevant resources, combined via a broad based intrusion alert system and architecture, adaptable/tunable for a spectrum of applications like, attack predictions in the context of vulnerabilities, security alerts in IoT/SCADA, insider attack correlations etc. To realize properties of speed and accuracy using intelligence from a spectrum of resources, use cognitive security solutions using AI/Deep Learning Systems. This project also envisages the development of techniques of privacy-preserving merging/integrating different datasets and privacy preservation training.
 |
Virendra Singh obtained Ph.D in Computer Science from Nara Institute of Science and Technology (NAIST), Nara, Japan. Currently, he is serving as a faculty member at Indian Institute of Technology (IIT) Bombay jointly with the Dept. of Electrical Engineering, and the Dept. of Computer Science and Engineering. Prior to join IIT Bombay, he served as a faculty member at Supercomputer Education and Research Centre (current Computational and Data Science department), Indian Institute of Science (IISc), Bangalore from 2007 to 2011. He also served Central Electronics Engineering Research Institute (CEERI), Pilani, as a Scientist from 1997 to 2007. His research interests are VLSI Design, verification and Test, High Performance Computer Architecture, Cyber security, cyber physical cognitive systems, trustworthy AI, formal verification. He has published about 195 research papers in various journals and international conferences. He is a convener of India-Japan joint research hub on Trustable cyber physical cognitive systems. He is leading a major project on development of AI powered adaptive cyber defence systems funded by government of India. |
Industrial talks
Designing market ready energy efficient silicon in the first shot
Speaker: Marcus Pietzsch (Racyics GmbH., Germany)
Time to market is key for the success of start-up technologies and groundbreaking new ideas from academic.
Being able to unwrap and showcase the full potential and performance of innovative solutions in integrated silicon introduces the need to deal with the multidimensional, complex challenges of SoC design. This talk presents a disruptive approach to overcome these struggles.
"makeChip" is enabling inventors to keep focus on their core IP while being able to demonstrate PPA (Power, Performance, Area) optimization at product level in the first shot. Technical approaches for designing first time right ultra low power SoC will be presented and discussed along example success stories.
Marcus Pietzsch studied electrical engineering at the Technical University Dresden. He was working in academic and industrial IP and chip design within different domains such as communication, medical or automotive. In 2022, he joined Racyics GmbH as "Head of SoC Design".
The Czech Republic and Its Active Contribution to International Semiconductor Strategy Activities
Speaker: Milan Semmler (UJP Praha a.s., Czech Rep.)
The Czech Republic, as one of the developed European economies, is striving to rapidly engage in the dynamically evolving activities within the semiconductor technology sector. The European Union has set ambitious objectives to significantly strengthen its current not so strong position in this market. To achieve this, the EU has committed to substantial investments in this sector and aims to coordinate major projects across Europe. With significant contributions from the Czech EU Presidency, the key document ChipAct was approved, featuring a group of major projects in IPCEI ME/CT (the Important Projects of Common European Interest). This lecture aims to provide a concise overview of how national entities are involved in this new strategy and, through a specific example, demonstrate what the Czech Republic can contribute to the collective European semiconductor initiative.
Milan Semmler, a graduate of the Faculty of Nuclear Sciences and Physical Engineering at the Czech Technical University in Prague, Department of Dosimetry and Application of Ionizing Radiation. After his studies, he worked at the Nuclear Research Institute in the field of neutron radiography. After 1989, he moved to the private sector and co-founded CHEMCOMEX PRAHA a.s., a company that has implemented dozens of projects at nuclear power plants. He led the development team for the primary monitoring system of VVER power plants. After 2000, he focused on the modernization of radionuclide irradiators for the treatment of cancer patients produced at UJP PRAHA a.s., where he still serves as a board member responsible for the company's research and development activities. He was appointed Vice President for Radiation-Resistant Microelectronics in the Czech National Semiconductor Cluster.
Progressive methods of driving permanent magnet synchronous motors (PMSM) with advanced algorithms and features
Speaker: Ondřej Holý (STMicroelectronics, Czech Rep.)
Field Oriented Control (FOC) is a very well-known technique used to drive permanent magnet synchronous motors (PMSM) for many years. It has been adapted by many developers and is used widely across many different applications with PMSM. Some of the applications require dedicated features, such as a control of start-up from zero speed, Start-up On-The-Fly (OTF), Maximum Torque Per Ampere (MTPA), Discontinuous PWM (DPWM) and many others. Those are not coming by default with the FOC technique but require advanced algorithms and techniques. In this workshop I will explain exclusively various advanced algorithms and techniques enabling such a features, including presentation of tools and resources that will ease their evaluation and implementation into own application use case. Benefits, resources constrains, and limits will be covered as well.
Ondřej Holý joined STMicroelectronics in 2014 as a Microcontroller Support Application Engineer. Before joining STMicroelectronics, Ondřej worked as a hardware and software development engineer using a wide range of microcontrollers including STM32. Ondrej is responsible for supporting clients in the EMEA region, providing guidance and training on STM32 and Motor Control.
Assessing Computation Efficiency in Embedded Systems
Speaker: Martin Daněk (daiteq, Czech Rep.)
Compared to commercial use, embedded systems for use in space have to consider additional design criteria, out of which perhaps the most important are radiation tolerance and power efficiency. The talk will present a number of metrics that can be used for assessment of computation efficiency, covering implementations ranging from dedicated hardware accelerators to custom processor instructions.
Keynotes
Colorful like a Chameleon: (In)Security of Wireless Access Control Systems
Speakers: Timo Kasper (Ruhr-University, Bochum, Germany; Kasper&Oswald GmbH.) and Tomáš Přeučil (FIT, CTU in Prague)
Wireless embedded devices have become omnipresent in applications such
as access control (to doors or to PCs), identification, and payments.
The talk reviews the security of several commercial devices that
typically employ cryptographic mechanisms as a protection against
ill-intended usage or to prevent unauthorized access. A combination of
side-channel attacks, reverse-engineering and mathematical cryptanalysis
helps to reveal and exploit weaknesses in the systems that for example
allow opening secured doors in seconds. At hand of real-world examples
and live demos, the implications of a key extraction for the security of
the respective contactless application are illustrated. As a powerful
tool for security-analyzing and pentesting NFC and RFID systems, the
open-source project “ChameleonMini” is presented: Besides
virtualization and emulation of contactless cards, the device allows to
log the NFC communication, and in its latest Revision G acts as an
active RFID reader to copy contactless cards on-the-fly.
Dr.-Ing. Timo Kasper is executive director of Kasper&Oswald GmbH (KAOS),
founded in 2012 together with Prof. Dr.-Ing. David Oswald, offering
innovative products and various services for (embedded) security
engineering. Timo has studied electrical engineering and information
technology at the Ruhr-University Bochum, Germany and at the University
of Sheffield, UK. His Diploma thesis (2006) and his PhD thesis (2012)
were awarded with a first prize in IT Security. Timo’s field of
expertise covers the security of embedded cryptographic systems, such as
smartcards, RFID and other (wireless) technology, including penetration
testing and implementation attacks.
Tomáš Přeučil, MSc. is a PhD student at the Faculty of Information Technology (FIT) at the Czech Technical University in Prague. His research focuses on the security of pervasive devices including access control systems and RFID card security, as well as attacks on non-IP-based networks.
Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits?
Speaker: Andreas Steininger (Vienna University of Technology, Austria)
While the synchrony obtained by a global clock simplifies design and implementation of digital circuits considerably, it also constitutes a strong assumption. This becomes perceivable by the clock distribution problems in high-speed circuits, but also by the uncontrolled error behavior that synchronous circuits usually exhibit upon even a small timing violation. Due to their much more flexible and self-regulated timing, asynchronous circuits do not need a sophisticated clock tree and can accommodate timing variations and delay-related faults naturally. In this talk we will survey approaches to complement this important time-domain property though explicit value-domain fault-tolerance provisions on coding- and circuit-level. In addition, we will investigate how the fail-stop property inherent to asynchronous circuits can be leveraged for easy recovery after repair of a permanent fault, and hence forms an interesting foundation for building self-repairing circuits.
Andreas Steininger studied Electrical Engineering at TU Wien where he also finished his PhD thesis in 1994, and is now working as an Associate Professor at the Department of Computer Engineering. He has been involved in many industrial and scientific projects concerned with real-time communication networks, the design of fault-tolerant / radiation-tolerant computer architectures and their evaluation by means of fault-injection, and testing. His current research focuses on asynchronous (“clockless”) logic design, timing-domain interfacing, metastability, and GALS architectures. He has published over 190 papers in journals and at international conferences and is co-inventor of over 10 patents. He has supervised more than 20 successful PhD theses and serves as the Director for the Vienna PhD School of Informatics and as chair of the Doctoral College Resilient Embedded Systems. Three of his master students have been winners of the faculty's highly competitive "Distinguished Young Alumnus Award" for the best diploma thesis.
Digital simulator: from the RTL to the full chip simulations of a low power SoC ASIC
Speaker: Jakub Šťastný (ASICentrum, s.r.o.)
Digital simulator is the basic tool to examine the behavior of the designed digital block. However, digital simulator can support designer's work also beyond the purely digital world - the whole ASIC can be modeled in it on the system level including analog blocks and power supply networks. During the talk we will discuss challenges brought by the full low-power SoC ASIC simulation and present a handful of case studies how we utilized the capabilities of a modern digital simulator.
Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple senzor chips to SoC systems.
Security Issues in Cyber Physical Cognitive Systems
Speaker: Virendra Singh (Indian Institute of Technology Bombay, Mumbai, India)
Migration to Society 5.0 has mandated to go for Industry 5.0 whose priority is to utilize human and machines synergistically. In order to achieve the above stated objective, Cyber Physical Systems (CPS) has become the central part of the Industry 5.0. Industry 5.0 demands cognitive computing along with the Cyber Physical Systems. Industry 5.0 aims at utilizing human and machine synergistically.
On the other hand, with sophisticated cyber attacks all over the world, it is clear that the attackers are well-funded through organized crimes, nation–support, etc. Thus, it has become important to address cyber threat intelligence to prevent some of the ulterior motives of the attackers to use attacks as weapons, in particular, when most of the public infrastructures are driven by sophisticated IT systems and further with the policy of building several smart-cities to address various societal issues. The latter naturally will lead to growth of Internet of Things (IoT), which in turn will increase the attack surface of the underlying infrastructure due to their vulnerabilities, malware susceptibility, and an emergence of denial-of-service (DoS) attacks will be acutely felt. Therefore the system must aims at the infrastructures with proactive sensing of cyber-physical systems using data from physical sensors and integrated from other relevant resources, combined via a broad based intrusion alert system and architecture, adaptable/tunable for a spectrum of applications like, attack predictions in the context of vulnerabilities, security alerts in IoT/SCADA, insider attack correlations etc. To realize properties of speed and accuracy using intelligence from a spectrum of resources, use cognitive security solutions using AI/Deep Learning Systems. This project also envisages the development of techniques of privacy-preserving merging/integrating different datasets and privacy preservation training.
|
Virendra Singh obtained Ph.D in Computer Science from Nara Institute of Science and Technology (NAIST), Nara, Japan. Currently, he is serving as a faculty member at Indian Institute of Technology (IIT) Bombay jointly with the Dept. of Electrical Engineering, and the Dept. of Computer Science and Engineering. Prior to join IIT Bombay, he served as a faculty member at Supercomputer Education and Research Centre (current Computational and Data Science department), Indian Institute of Science (IISc), Bangalore from 2007 to 2011. He also served Central Electronics Engineering Research Institute (CEERI), Pilani, as a Scientist from 1997 to 2007. His research interests are VLSI Design, verification and Test, High Performance Computer Architecture, Cyber security, cyber physical cognitive systems, trustworthy AI, formal verification. He has published about 195 research papers in various journals and international conferences. He is a convener of India-Japan joint research hub on Trustable cyber physical cognitive systems. He is leading a major project on development of AI powered adaptive cyber defence systems funded by government of India. |
Industrial talks
Designing market ready energy efficient silicon in the first shot
Speaker: Marcus Pietzsch (Racyics GmbH., Germany)
Time to market is key for the success of start-up technologies and groundbreaking new ideas from academic.
Being able to unwrap and showcase the full potential and performance of innovative solutions in integrated silicon introduces the need to deal with the multidimensional, complex challenges of SoC design. This talk presents a disruptive approach to overcome these struggles.
"makeChip" is enabling inventors to keep focus on their core IP while being able to demonstrate PPA (Power, Performance, Area) optimization at product level in the first shot. Technical approaches for designing first time right ultra low power SoC will be presented and discussed along example success stories.
Marcus Pietzsch studied electrical engineering at the Technical University Dresden. He was working in academic and industrial IP and chip design within different domains such as communication, medical or automotive. In 2022, he joined Racyics GmbH as "Head of SoC Design".
The Czech Republic and Its Active Contribution to International Semiconductor Strategy Activities
Speaker: Milan Semmler (UJP Praha a.s., Czech Rep.)
The Czech Republic, as one of the developed European economies, is striving to rapidly engage in the dynamically evolving activities within the semiconductor technology sector. The European Union has set ambitious objectives to significantly strengthen its current not so strong position in this market. To achieve this, the EU has committed to substantial investments in this sector and aims to coordinate major projects across Europe. With significant contributions from the Czech EU Presidency, the key document ChipAct was approved, featuring a group of major projects in IPCEI ME/CT (the Important Projects of Common European Interest). This lecture aims to provide a concise overview of how national entities are involved in this new strategy and, through a specific example, demonstrate what the Czech Republic can contribute to the collective European semiconductor initiative.
Milan Semmler, a graduate of the Faculty of Nuclear Sciences and Physical Engineering at the Czech Technical University in Prague, Department of Dosimetry and Application of Ionizing Radiation. After his studies, he worked at the Nuclear Research Institute in the field of neutron radiography. After 1989, he moved to the private sector and co-founded CHEMCOMEX PRAHA a.s., a company that has implemented dozens of projects at nuclear power plants. He led the development team for the primary monitoring system of VVER power plants. After 2000, he focused on the modernization of radionuclide irradiators for the treatment of cancer patients produced at UJP PRAHA a.s., where he still serves as a board member responsible for the company's research and development activities. He was appointed Vice President for Radiation-Resistant Microelectronics in the Czech National Semiconductor Cluster.
Progressive methods of driving permanent magnet synchronous motors (PMSM) with advanced algorithms and features
Speaker: Ondřej Holý (STMicroelectronics, Czech Rep.)
Field Oriented Control (FOC) is a very well-known technique used to drive permanent magnet synchronous motors (PMSM) for many years. It has been adapted by many developers and is used widely across many different applications with PMSM. Some of the applications require dedicated features, such as a control of start-up from zero speed, Start-up On-The-Fly (OTF), Maximum Torque Per Ampere (MTPA), Discontinuous PWM (DPWM) and many others. Those are not coming by default with the FOC technique but require advanced algorithms and techniques. In this workshop I will explain exclusively various advanced algorithms and techniques enabling such a features, including presentation of tools and resources that will ease their evaluation and implementation into own application use case. Benefits, resources constrains, and limits will be covered as well.
Ondřej Holý joined STMicroelectronics in 2014 as a Microcontroller Support Application Engineer. Before joining STMicroelectronics, Ondřej worked as a hardware and software development engineer using a wide range of microcontrollers including STM32. Ondrej is responsible for supporting clients in the EMEA region, providing guidance and training on STM32 and Motor Control.
Assessing Computation Efficiency in Embedded Systems
Speaker: Martin Daněk (daiteq, Czech Rep.)
Compared to commercial use, embedded systems for use in space have to consider additional design criteria, out of which perhaps the most important are radiation tolerance and power efficiency. The talk will present a number of metrics that can be used for assessment of computation efficiency, covering implementations ranging from dedicated hardware accelerators to custom processor instructions.