PESW 2024
PESW 2024
The 12th Prague Embedded Systems Workshop
June 27 – 29, 2024
Horoměřice, Czech Republic
PESW 2024
The 12th Prague Embedded Systems Workshop
June 27 – 29, 2024
Horoměřice, Czech Republic

Keynotes

Colorful like a Chameleon: (In)Security of Wireless Access Control Systems

Speakers: Timo Kasper (Ruhr-University, Bochum, Germany; Kasper&Oswald GmbH.) and Tomáš Přeučil (FIT, CTU in Prague)

Wireless embedded devices have become omnipresent in applications such as access control (to doors or to PCs), identification, and payments. The talk reviews the security of several commercial devices that typically employ cryptographic mechanisms as a protection against ill-intended usage or to prevent unauthorized access. A combination of side-channel attacks, reverse-engineering and mathematical cryptanalysis helps to reveal and exploit weaknesses in the systems that for example allow opening secured doors in seconds. At hand of real-world examples and live demos, the implications of a key extraction for the security of the respective contactless application are illustrated. As a powerful tool for security-analyzing and pentesting NFC and RFID systems, the open-source project “ChameleonMini” is presented: Besides virtualization and emulation of contactless cards, the device allows to log the NFC communication, and in its latest Revision G acts as an active RFID reader to copy contactless cards on-the-fly.

Timo Kasper

Dr.-Ing. Timo Kasper is executive director of Kasper&Oswald GmbH (KAOS), founded in 2012 together with Prof. Dr.-Ing. David Oswald, offering innovative products and various services for (embedded) security engineering. Timo has studied electrical engineering and information technology at the Ruhr-University Bochum, Germany and at the University of Sheffield, UK. His Diploma thesis (2006) and his PhD thesis (2012) were awarded with a first prize in IT Security. Timo’s field of expertise covers the security of embedded cryptographic systems, such as smartcards, RFID and other (wireless) technology, including penetration testing and implementation attacks.

Tomáš Přeučil

Tomáš Přeučil, MSc. is a PhD student at the Faculty of Information Technology (FIT) at the Czech Technical University in Prague. His research focuses on the security of pervasive devices including access control systems and RFID card security, as well as attacks on non-IP-based networks.


Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits?

Speaker: Andreas Steininger (Vienna University of Technology, Austria)

While the synchrony obtained by a global clock simplifies design and implementation of digital circuits considerably, it also constitutes a strong assumption. This becomes perceivable by the clock distribution problems in high-speed circuits, but also by the uncontrolled error behavior that synchronous circuits usually exhibit upon even a small timing violation. Due to their much more flexible and self-regulated timing, asynchronous circuits do not need a sophisticated clock tree and can accommodate timing variations and delay-related faults naturally. In this talk we will survey approaches to complement this important time-domain property though explicit value-domain fault-tolerance provisions on coding- and circuit-level. In addition, we will investigate how the fail-stop property inherent to asynchronous circuits can be leveraged for easy recovery after repair of a permanent fault, and hence forms an interesting foundation for building self-repairing circuits.

Andreas Steininger

Andreas Steininger studied Electrical Engineering at TU Wien where he also finished his PhD thesis in 1994, and is now working as an Associate Professor at the Department of Computer Engineering. He has been involved in many industrial and scientific projects concerned with real-time communication networks, the design of fault-tolerant / radiation-tolerant computer architectures and their evaluation by means of fault-injection, and testing. His current research focuses on asynchronous (“clockless”) logic design, timing-domain interfacing, metastability, and GALS architectures. He has published over 190 papers in journals and at international conferences and is co-inventor of over 10 patents. He has supervised more than 20 successful PhD theses and serves as the Director for the Vienna PhD School of Informatics and as chair of the Doctoral College Resilient Embedded Systems. Three of his master students have been winners of the faculty's highly competitive "Distinguished Young Alumnus Award" for the best diploma thesis.


Digital simulator: from the RTL to the full chip simulations of a low power SoC ASIC

Speaker: Jakub Šťastný (ASICentrum, s.r.o.)

Digital simulator is the basic tool to examine the behavior of the designed digital block. However, digital simulator can support designer's work also beyond the purely digital world - the whole ASIC can be modeled in it on the system level including analog blocks and power supply networks. During the talk we will discuss challenges brought by the full low-power SoC ASIC simulation and present a handful of case studies how we utilized the capabilities of a modern digital simulator.

Jakub Šťastný

Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple senzor chips to SoC systems.


Industrial talks

Designing market ready energy efficient silicon in the first shot

Speaker: Marcus Pietzsch (Racyics GmbH., Germany)

Time to market is key for the success of start-up technologies and groundbreaking new ideas from academic.
Being able to unwrap and showcase the full potential and performance of innovative solutions in integrated silicon introduces the need to deal with the multidimensional, complex challenges of SoC design. This talk presents a disruptive approach to overcome these struggles.
"makeChip" is enabling inventors to keep focus on their core IP while being able to demonstrate PPA (Power, Performance, Area) optimization at product level in the first shot. Technical approaches for designing first time right ultra low power SoC will be presented and discussed along example success stories.

Marcus Pietzsch

Marcus Pietzsch studied electrical engineering at the Technical University Dresden. He was working in academic and industrial IP and chip design within different domains such as communication, medical or automotive. In 2022, he joined Racyics GmbH as "Head of SoC Design".



Keynotes

Colorful like a Chameleon: (In)Security of Wireless Access Control Systems

Speakers: Timo Kasper (Ruhr-University, Bochum, Germany; Kasper&Oswald GmbH.) and Tomáš Přeučil (FIT, CTU in Prague)

Wireless embedded devices have become omnipresent in applications such as access control (to doors or to PCs), identification, and payments. The talk reviews the security of several commercial devices that typically employ cryptographic mechanisms as a protection against ill-intended usage or to prevent unauthorized access. A combination of side-channel attacks, reverse-engineering and mathematical cryptanalysis helps to reveal and exploit weaknesses in the systems that for example allow opening secured doors in seconds. At hand of real-world examples and live demos, the implications of a key extraction for the security of the respective contactless application are illustrated. As a powerful tool for security-analyzing and pentesting NFC and RFID systems, the open-source project “ChameleonMini” is presented: Besides virtualization and emulation of contactless cards, the device allows to log the NFC communication, and in its latest Revision G acts as an active RFID reader to copy contactless cards on-the-fly.

Timo Kasper

Dr.-Ing. Timo Kasper is executive director of Kasper&Oswald GmbH (KAOS), founded in 2012 together with Prof. Dr.-Ing. David Oswald, offering innovative products and various services for (embedded) security engineering. Timo has studied electrical engineering and information technology at the Ruhr-University Bochum, Germany and at the University of Sheffield, UK. His Diploma thesis (2006) and his PhD thesis (2012) were awarded with a first prize in IT Security. Timo’s field of expertise covers the security of embedded cryptographic systems, such as smartcards, RFID and other (wireless) technology, including penetration testing and implementation attacks.

Tomáš Přeučil

Tomáš Přeučil, MSc. is a PhD student at the Faculty of Information Technology (FIT) at the Czech Technical University in Prague. His research focuses on the security of pervasive devices including access control systems and RFID card security, as well as attacks on non-IP-based networks.


Asynchronous Circuits – Old Iron or Enabler for a New Resilience Level of Digital Circuits?

Speaker: Andreas Steininger (Vienna University of Technology, Austria)

While the synchrony obtained by a global clock simplifies design and implementation of digital circuits considerably, it also constitutes a strong assumption. This becomes perceivable by the clock distribution problems in high-speed circuits, but also by the uncontrolled error behavior that synchronous circuits usually exhibit upon even a small timing violation. Due to their much more flexible and self-regulated timing, asynchronous circuits do not need a sophisticated clock tree and can accommodate timing variations and delay-related faults naturally. In this talk we will survey approaches to complement this important time-domain property though explicit value-domain fault-tolerance provisions on coding- and circuit-level. In addition, we will investigate how the fail-stop property inherent to asynchronous circuits can be leveraged for easy recovery after repair of a permanent fault, and hence forms an interesting foundation for building self-repairing circuits.

Andreas Steininger

Andreas Steininger studied Electrical Engineering at TU Wien where he also finished his PhD thesis in 1994, and is now working as an Associate Professor at the Department of Computer Engineering. He has been involved in many industrial and scientific projects concerned with real-time communication networks, the design of fault-tolerant / radiation-tolerant computer architectures and their evaluation by means of fault-injection, and testing. His current research focuses on asynchronous (“clockless”) logic design, timing-domain interfacing, metastability, and GALS architectures. He has published over 190 papers in journals and at international conferences and is co-inventor of over 10 patents. He has supervised more than 20 successful PhD theses and serves as the Director for the Vienna PhD School of Informatics and as chair of the Doctoral College Resilient Embedded Systems. Three of his master students have been winners of the faculty's highly competitive "Distinguished Young Alumnus Award" for the best diploma thesis.


Digital simulator: from the RTL to the full chip simulations of a low power SoC ASIC

Speaker: Jakub Šťastný (ASICentrum, s.r.o.)

Digital simulator is the basic tool to examine the behavior of the designed digital block. However, digital simulator can support designer's work also beyond the purely digital world - the whole ASIC can be modeled in it on the system level including analog blocks and power supply networks. During the talk we will discuss challenges brought by the full low-power SoC ASIC simulation and present a handful of case studies how we utilized the capabilities of a modern digital simulator.

Jakub Šťastný

Jakub Šťastný studied at the Czech Technical Unverisity in Prague, Faculty of Electrotechnical engineering. He has been working for ASICentrum spol. s r.o. (EM Microelectronic) since 2002, currently at the position of the ASICentrum's Motion and Optical Sensing department leader. During his career he has been working on tens of custom ultra low-power ASIC projects mainly as project manager and digital designer, dealing with devices ranging in size from simple senzor chips to SoC systems.


Industrial talks

Designing market ready energy efficient silicon in the first shot

Speaker: Marcus Pietzsch (Racyics GmbH., Germany)

Time to market is key for the success of start-up technologies and groundbreaking new ideas from academic.
Being able to unwrap and showcase the full potential and performance of innovative solutions in integrated silicon introduces the need to deal with the multidimensional, complex challenges of SoC design. This talk presents a disruptive approach to overcome these struggles.
"makeChip" is enabling inventors to keep focus on their core IP while being able to demonstrate PPA (Power, Performance, Area) optimization at product level in the first shot. Technical approaches for designing first time right ultra low power SoC will be presented and discussed along example success stories.

Marcus Pietzsch

Marcus Pietzsch studied electrical engineering at the Technical University Dresden. He was working in academic and industrial IP and chip design within different domains such as communication, medical or automotive. In 2022, he joined Racyics GmbH as "Head of SoC Design".