PESW 2022
PESW 2022
The 10th Prague Embedded Systems Workshop
June 30 - July 2, 2022
Horoměřice, Czech Republic
PESW 2022
The 10th Prague Embedded Systems Workshop
June 30 - July 2, 2022
Horoměřice, Czech Republic

Keynotes

Networkmetrics for Network Monitoring and Security

Speaker: José Camacho Páez, University of Granada, Spain

Multivariate analysis has been recognized as an outstanding Machine Learning approach in several domains, including industrial monitoring, marketing, weather modeling, bioinformatics, and many more. In this methodology, visualization, interpretation, and data interaction are principal tools for an analyst to understand the problem the data reflects. This locates multivariate analysis as one approach within the area of interpretable machine learning, also referred to as eXplanaible AI (XAI), which has raised a lot of attention in recent years.
Prof. Camacho coined the term networkmetrics one decade ago, referring to the use of multivariate analysis and other interpretable machine learning tools in network applications. It stands for the combination of the application domain (network engineering) and the suffix "-metrics", inherited from other disciplines where interpretable multivariate analysis has been widely adopted, both in academia and industry. This is the case of psychometrics in psychology, econometrics in economy or chemometrics in chemistry. As for today, those areas are so mature that there is a wide body of research with internationally renowned journals, and companies demand specific job positions of psychometricians, econometricians and chemometricians, acknowledging their added value in problem solving. Data interpretability is key in all –metrics disciplines: the data analyst employs multivariate analysis to understand patterns and gain insights into the data, rather than as a black-box model. Network engineering shares with psychology, economy or chemistry the same need for interpretable multivariate analysis, since tasks like network monitoring and troubleshooting, network design and optimization, or network security, have essentially a multivariate nature, and require models that are interpretable by engineers in a network operator center (NOC) or network security center (NSC).
This talk will motivate the use of multivariate analysis in network problems using real examples.

José Camacho Páez

José Camacho is full professor with the Department of Signal Theory, Networking and Communications and researcher in the Information and Communication Technologies Research Centre, CITIC for its initials in Spanish, both at the University of Granada, Spain. He holds a degree in Computer Science from the University of Granada (2003) and a Ph.D. from the Technical University of Valencia (2007). His Ph.D. was awarded with the second Rosina Ribalta Prize to the best Ph.D. projects in the field of Information and Communication Technologies (ICT) from the EPSON Foundation, and with the D.L. Massart Award in Chemometrics from the Belgian Chemometrics Society. He worked as a post-doctoral fellow at the University of Girona, granted by the Juan de la Cierva program, and was a Fulbright fellow in 2018 at the Dartmouth College, USA. His research interests include exploratory data analysis, machine learning and inferential statistics with multivariate techniques applied to data of very different nature, including personalized medicine, molecular biology, chemistry and communication networks. He has authored more than 50 publications in impact journals (JCR), and a similar number of publications in conferences and workshops. He has participated in 20 research projects and collaborate actively in three open software projects in Github.

Reliability evaluation of general purpose and AI processing architectures

Speaker: Prof. Dr. Miloš Krstić, University of Potsdam, Germany, Leibniz Institute for High Performance Microelectronics (IHP)

In many applications, such as space or automotive, the reliability plays significant role. In addition to usual properties, such as performance and power consumption, such applications need to fulfil additional reliability requirements.
Such evaluation is usually connected with tedious fault injection campaigns that need to be performed at the netlist level. In this talk the alternatives will be discussed, including the use of machine learning for the extraction of reliability critical parameters from digital circuits.
Additionally, the reliability evaluation has been performed on the various processing architectures. Major focus is on AI accelerator architectures, and with this respect two orthogonal technologies have been investigated. On one hand, the classical digital approach has been investigated on open access NVDLA platform. As an alternative, emerging RRAM technology and corresponding crossbar architectures are frequently evaluated in the context of AI acceleration. In this talk, we will indicate the potential of those approach, possibilities for system level verification, but also the reliability threats, such as read disturb.

Miloš Krstić

Prof. Dr. Milos Krstic received the Dr-Ing. degree in electronics from Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP, Frankfurt (Oder), Germany, where he leads the department System Architectures. From 2016 he is also professor for “Design and Test Methodology” at the University of Potsdam. For the last few years, his work was mainly focused on fault tolerant architectures and design methodologies for digital systems integration. Prof. Krstic has been managing many international and national R & D projects (GALAXY, EMPHASE, BB-KI-Chips, IC-NAO, ENROL, RTU-ASIC, SEPHY, DIFFERENT, VHiSSi, RESCUE, etc.). He is also leading and coordinating space activities at IHP. He has published more than 200 journal and conference papers, and registered 9 patents.


Advances in dependable image processing and deep learning

Speaker: Luca Cassano, Ph.D., Politecnico di Milano, Italy

There is great interest in employing Image Processing (IM) and Deep Lerning (DL) in a variety of application fields that expose safety- and mission-critical requirements. In these scenarios, it is crucial to assess the reliability of the computing system (composed of the application running on top of a processing platform), to adopt (if necessary) specific hardening techniques. Most of existing approaches for the reliability analysis and for the hardening of these applications still rely on the classical coccrect/corrupted output identification. Nevertheless, when dealing with IM and DL applications designers and safety-engineers have to keep in mind that the application itself may benefit from an intrinsic degree of resilience to faults. Indeed, cases may exist where the final application is still able to correctly carry out its task although some intermediate results are partially corrupted. Therefore, it may be beneficial to analyse the relibility of the application and to harden the system based on the more advanced usable/unusable output classification paradigm that has recently been proposed. The talk will present a number of advanced solutions for the reliability analysis and the hardening of IM and DL applications accelerated onto embedded CPUs and GPUs.

Luca Cassano
Luca Cassano is a Tenure-Track Assistant Professor at Politecnico di Milano, Italy. He received the B.S., M.S. and Ph.D. degrees in Computer Engineering from the University of Pisa, Italy. His research activity focuses on the definition of innovative techniques for fault simulation, testing, untestability analysis, diagnosis, and verification of fault tolerant and secure digital circuits and systems. He published more than 60 papers in refereed international journals and conferences. He served as program chair for DFTS 2021 and he is currently the program chair of DFTS 2022 and he serves in the organizing and program committees of several conferences on EDA, CAD and test (ETS, IOLTS, DDECS, DSD). He is associate editor of Integration, the VLSI Journal and of the Journal of Electronic Testing. With his Ph.D. thesis, titled "Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs", he won the European semifinals of the 2014 TTTC's E. J. McCluskey Doctoral Thesis Award.

Keynotes

Networkmetrics for Network Monitoring and Security

Speaker: José Camacho Páez, University of Granada, Spain

Multivariate analysis has been recognized as an outstanding Machine Learning approach in several domains, including industrial monitoring, marketing, weather modeling, bioinformatics, and many more. In this methodology, visualization, interpretation, and data interaction are principal tools for an analyst to understand the problem the data reflects. This locates multivariate analysis as one approach within the area of interpretable machine learning, also referred to as eXplanaible AI (XAI), which has raised a lot of attention in recent years.
Prof. Camacho coined the term networkmetrics one decade ago, referring to the use of multivariate analysis and other interpretable machine learning tools in network applications. It stands for the combination of the application domain (network engineering) and the suffix "-metrics", inherited from other disciplines where interpretable multivariate analysis has been widely adopted, both in academia and industry. This is the case of psychometrics in psychology, econometrics in economy or chemometrics in chemistry. As for today, those areas are so mature that there is a wide body of research with internationally renowned journals, and companies demand specific job positions of psychometricians, econometricians and chemometricians, acknowledging their added value in problem solving. Data interpretability is key in all –metrics disciplines: the data analyst employs multivariate analysis to understand patterns and gain insights into the data, rather than as a black-box model. Network engineering shares with psychology, economy or chemistry the same need for interpretable multivariate analysis, since tasks like network monitoring and troubleshooting, network design and optimization, or network security, have essentially a multivariate nature, and require models that are interpretable by engineers in a network operator center (NOC) or network security center (NSC).
This talk will motivate the use of multivariate analysis in network problems using real examples.

José Camacho Páez

José Camacho is full professor with the Department of Signal Theory, Networking and Communications and researcher in the Information and Communication Technologies Research Centre, CITIC for its initials in Spanish, both at the University of Granada, Spain. He holds a degree in Computer Science from the University of Granada (2003) and a Ph.D. from the Technical University of Valencia (2007). His Ph.D. was awarded with the second Rosina Ribalta Prize to the best Ph.D. projects in the field of Information and Communication Technologies (ICT) from the EPSON Foundation, and with the D.L. Massart Award in Chemometrics from the Belgian Chemometrics Society. He worked as a post-doctoral fellow at the University of Girona, granted by the Juan de la Cierva program, and was a Fulbright fellow in 2018 at the Dartmouth College, USA. His research interests include exploratory data analysis, machine learning and inferential statistics with multivariate techniques applied to data of very different nature, including personalized medicine, molecular biology, chemistry and communication networks. He has authored more than 50 publications in impact journals (JCR), and a similar number of publications in conferences and workshops. He has participated in 20 research projects and collaborate actively in three open software projects in Github.

Reliability evaluation of general purpose and AI processing architectures

Speaker: Prof. Dr. Miloš Krstić, University of Potsdam, Germany, Leibniz Institute for High Performance Microelectronics (IHP)

In many applications, such as space or automotive, the reliability plays significant role. In addition to usual properties, such as performance and power consumption, such applications need to fulfil additional reliability requirements.
Such evaluation is usually connected with tedious fault injection campaigns that need to be performed at the netlist level. In this talk the alternatives will be discussed, including the use of machine learning for the extraction of reliability critical parameters from digital circuits.
Additionally, the reliability evaluation has been performed on the various processing architectures. Major focus is on AI accelerator architectures, and with this respect two orthogonal technologies have been investigated. On one hand, the classical digital approach has been investigated on open access NVDLA platform. As an alternative, emerging RRAM technology and corresponding crossbar architectures are frequently evaluated in the context of AI acceleration. In this talk, we will indicate the potential of those approach, possibilities for system level verification, but also the reliability threats, such as read disturb.

Miloš Krstić

Prof. Dr. Milos Krstic received the Dr-Ing. degree in electronics from Brandenburg University of Technology, Cottbus, Germany in 2006. Since 2001 he has been with IHP, Frankfurt (Oder), Germany, where he leads the department System Architectures. From 2016 he is also professor for “Design and Test Methodology” at the University of Potsdam. For the last few years, his work was mainly focused on fault tolerant architectures and design methodologies for digital systems integration. Prof. Krstic has been managing many international and national R & D projects (GALAXY, EMPHASE, BB-KI-Chips, IC-NAO, ENROL, RTU-ASIC, SEPHY, DIFFERENT, VHiSSi, RESCUE, etc.). He is also leading and coordinating space activities at IHP. He has published more than 200 journal and conference papers, and registered 9 patents.


Advances in dependable image processing and deep learning

Speaker: Luca Cassano, Ph.D., Politecnico di Milano, Italy

There is great interest in employing Image Processing (IM) and Deep Lerning (DL) in a variety of application fields that expose safety- and mission-critical requirements. In these scenarios, it is crucial to assess the reliability of the computing system (composed of the application running on top of a processing platform), to adopt (if necessary) specific hardening techniques. Most of existing approaches for the reliability analysis and for the hardening of these applications still rely on the classical coccrect/corrupted output identification. Nevertheless, when dealing with IM and DL applications designers and safety-engineers have to keep in mind that the application itself may benefit from an intrinsic degree of resilience to faults. Indeed, cases may exist where the final application is still able to correctly carry out its task although some intermediate results are partially corrupted. Therefore, it may be beneficial to analyse the relibility of the application and to harden the system based on the more advanced usable/unusable output classification paradigm that has recently been proposed. The talk will present a number of advanced solutions for the reliability analysis and the hardening of IM and DL applications accelerated onto embedded CPUs and GPUs.

Luca Cassano
Luca Cassano is a Tenure-Track Assistant Professor at Politecnico di Milano, Italy. He received the B.S., M.S. and Ph.D. degrees in Computer Engineering from the University of Pisa, Italy. His research activity focuses on the definition of innovative techniques for fault simulation, testing, untestability analysis, diagnosis, and verification of fault tolerant and secure digital circuits and systems. He published more than 60 papers in refereed international journals and conferences. He served as program chair for DFTS 2021 and he is currently the program chair of DFTS 2022 and he serves in the organizing and program committees of several conferences on EDA, CAD and test (ETS, IOLTS, DDECS, DSD). He is associate editor of Integration, the VLSI Journal and of the Journal of Electronic Testing. With his Ph.D. thesis, titled "Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs", he won the European semifinals of the 2014 TTTC's E. J. McCluskey Doctoral Thesis Award.