PESW 2019
PESW 2019
The 7th Prague Embedded Systems Workshop
June 27-29, 2019
Roztoky u Prahy, Czech Republic
PESW 2019
The 7th Prague Embedded Systems Workshop
June 27-29, 2019
Roztoky u Prahy, Czech Republic


PESW 2019 Program

The program is available here - printable PDF.


Thursday, June 27

9:00-10:00Registration
10:00-10:20Opening
10:20-11:10
(2x 25)
Session 1 - Fault Tolerance & Reliability. Chair: Robert Hülle
Ondřej Čekan, Jakub Podivínský, Jakub Lojda, Richard Pánek, Martin Krčma, and Zdeněk Kotásek: Smart Electronic Locks and Their Reliability
Karel Szurman and Zdeněk Kotásek: Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization
11:10-11:30Coffee break
11:30-12:30Keynote 1 - Elena-Ioana Vatajelu: Randomness in emerging technologies: Functional robustness vs. security
12:30-14:00Lunch
14:00-14:50
(2x 25)
Session 2 - Cryptosystems & Cryptanalysis. Chair: Vojtěch Miškovský
Josef Kokeš and Róbert Lórencz: Linear cryptanalysis and recovery of key bits in Baby Rijndael
Jan Říha, Jakub Klemsa, and Martin Novotný: Multiprecision Microcontroller-optimized ANSI C Library for Exotic Cryptosystems
14:50-15:10Coffee break
15:10-16:00
(2x 25)
Session 3 - Other. Chair: Karel Szurman
Tomasz Czech, Małgorzata Mazurkiewicz, Piotr Mróz, and Anna Pławiak-Mowna: Recognition of Semi-trailers on the basis of the image
Jakub Podivínský, Ondrej Čekan, Martin Krčma, Radek Burget, Tomáš Hruška, and Zdeněk Kotásek: Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study
16:00-???Walking tour to Únětice Brewery
Welcome beer

Friday, June 28

9:15-10:00Keynote 2 - Jan Kořenek: Hardware Acceleration Techniques for Network Monitoring and Security
10:00-10:10Jan Bělohoubek: Presentation of IEEE YP, introduction to the Student posters session
10:10-10:45Coffee break & student posters
10:45-12:00
(3x 25)
Session 4 - Network Monitoring. Chair: Tomáš Čejka
Petr Velan: The Future of Network Flow Monitoring
Karel Hynek, Tomáš Beneš, Tomáš Čejka, and Hana Kubátová: Future approaches to monitoring in high-speed backbone networks
Jiří Havránek, Tomáš Čejka, and Pavel Benáček: L7 capable flow exporter described in P4
12:00-13:30Lunch
13:30-14:45
(3x 25)
Session 5 - Traffic Processing and Analysis. Chair: Karel Hynek
Lukáš Huták: A New Generation of an IPFIX Collector
Milan Čermák: Trace-Share: Towards Provable Network Traffic Measurement and Analysis
Dominik Soukup, Tomáš Čejka, and Simon Stefunko: Multi-level Anomaly Detection in IoT Networks
14:45-15:30Coffee break & student posters
15:30-16:20
(2x 25)
Session 6 - Security. Chair: Josef Kokeš
Jan Bělohoubek and Robert Vik: Low-Cost CMOS Power Consumption Data Dependence Demonstrator Concept
Stanislav Jeřábek and Jan Schmidt: Analysis of the Dummy Rounds Scheme Optimizations
16:20-17:00Student contest results
17:00-???Dinner & bowling at the Academic hotel

Saturday, June 29

10:00-10:50
(2x 25)
Session 7 - Testing & Test Generation. Chair: Jan Bělohoubek
Vishal Gupta, Jimson Mathew, and Marco Ottavi: Health Monitoring and Fault Detection Using Memristive Switching Behavior in DSC Array
Robert Hülle, Petr Fišer, and Jan Schmidt: PBO-Based Fault Selection for Compact Test Generation
10:50-11:50Keynote 3 - Paolo Bernardi: Automotive testing challenges
11:50-12:10Closing
12:10Lunch

Posters Accepted for Presentation and Contest Results

All contestants obtained a STM DevBoard, the IEEE gift bag and free access to PESW.

Bachelor Theses
Author Title Institution Best Poster Award
Pavel Chytrý Visualization of telemetry data with holographic glasses FIT ČVUT
Pavel Dohnal Portable sount synthetizer with multitrack recording FIT ČVUT 2ndPrize; ASICentrum and CZ.NIC Award
Jakub Kyzek SmartHome design and implementation FIT ČVUT 1stPrize; CZ.NIC, NXP and STM Award
Master Theses
Author Title Institution Best Poster Award
Jan Říha Implementation and Effectiveness Evaluation of the VeraGreg Scheme on a Low-Cost Microcontroller FIT ČVUT
Paolo Calao Emulation-based Fault Injection of Transient Faults in Complex System-on-Chip Politecnico di Torino
Petr Socha SICAK: SIde-Channel Analysis toolKit FIT ČVUT
Enrico Rovere Automatic Generation of Functional Stress Programs with enhanced observability Politecnico di Torino 1stPrize; IEEE, CZ.NIC, NXP and STM Award
Jan Reznicek Hierarchical Dependability Models based on Non-Homogeneous Continuous Time Markov Chains FIT ČVUT 2ndPrize; ASICentrum, CZ.NIC, NXP and STM Award


PESW 2019 Program

The program is available here - printable PDF.


Thursday, June 27

9:00-10:00Registration
10:00-10:20Opening
10:20-11:10
(2x 25)
Session 1 - Fault Tolerance & Reliability. Chair: Robert Hülle
Ondřej Čekan, Jakub Podivínský, Jakub Lojda, Richard Pánek, Martin Krčma, and Zdeněk Kotásek: Smart Electronic Locks and Their Reliability
Karel Szurman and Zdeněk Kotásek: Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization
11:10-11:30Coffee break
11:30-12:30Keynote 1 - Elena-Ioana Vatajelu: Randomness in emerging technologies: Functional robustness vs. security
12:30-14:00Lunch
14:00-14:50
(2x 25)
Session 2 - Cryptosystems & Cryptanalysis. Chair: Vojtěch Miškovský
Josef Kokeš and Róbert Lórencz: Linear cryptanalysis and recovery of key bits in Baby Rijndael
Jan Říha, Jakub Klemsa, and Martin Novotný: Multiprecision Microcontroller-optimized ANSI C Library for Exotic Cryptosystems
14:50-15:10Coffee break
15:10-16:00
(2x 25)
Session 3 - Other. Chair: Karel Szurman
Tomasz Czech, Małgorzata Mazurkiewicz, Piotr Mróz, and Anna Pławiak-Mowna: Recognition of Semi-trailers on the basis of the image
Jakub Podivínský, Ondrej Čekan, Martin Krčma, Radek Burget, Tomáš Hruška, and Zdeněk Kotásek: Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study
16:00-???Walking tour to Únětice Brewery
Welcome beer

Friday, June 28

9:15-10:00Keynote 2 - Jan Kořenek: Hardware Acceleration Techniques for Network Monitoring and Security
10:00-10:10Jan Bělohoubek: Presentation of IEEE YP, introduction to the Student posters session
10:10-10:45Coffee break & student posters
10:45-12:00
(3x 25)
Session 4 - Network Monitoring. Chair: Tomáš Čejka
Petr Velan: The Future of Network Flow Monitoring
Karel Hynek, Tomáš Beneš, Tomáš Čejka, and Hana Kubátová: Future approaches to monitoring in high-speed backbone networks
Jiří Havránek, Tomáš Čejka, and Pavel Benáček: L7 capable flow exporter described in P4
12:00-13:30Lunch
13:30-14:45
(3x 25)
Session 5 - Traffic Processing and Analysis. Chair: Karel Hynek
Lukáš Huták: A New Generation of an IPFIX Collector
Milan Čermák: Trace-Share: Towards Provable Network Traffic Measurement and Analysis
Dominik Soukup, Tomáš Čejka, and Simon Stefunko: Multi-level Anomaly Detection in IoT Networks
14:45-15:30Coffee break & student posters
15:30-16:20
(2x 25)
Session 6 - Security. Chair: Josef Kokeš
Jan Bělohoubek and Robert Vik: Low-Cost CMOS Power Consumption Data Dependence Demonstrator Concept
Stanislav Jeřábek and Jan Schmidt: Analysis of the Dummy Rounds Scheme Optimizations
16:20-17:00Student contest results
17:00-???Dinner & bowling at the Academic hotel

Saturday, June 29

10:00-10:50
(2x 25)
Session 7 - Testing & Test Generation. Chair: Jan Bělohoubek
Vishal Gupta, Jimson Mathew, and Marco Ottavi: Health Monitoring and Fault Detection Using Memristive Switching Behavior in DSC Array
Robert Hülle, Petr Fišer, and Jan Schmidt: PBO-Based Fault Selection for Compact Test Generation
10:50-11:50Keynote 3 - Paolo Bernardi: Automotive testing challenges
11:50-12:10Closing
12:10Lunch

Posters Accepted for Presentation and Contest Results

All contestants obtained a STM DevBoard, the IEEE gift bag and free access to PESW.

Bachelor Theses
Author Title Institution Best Poster Award
Pavel Chytrý Visualization of telemetry data with holographic glasses FIT ČVUT
Pavel Dohnal Portable sount synthetizer with multitrack recording FIT ČVUT 2ndPrize; ASICentrum and CZ.NIC Award
Jakub Kyzek SmartHome design and implementation FIT ČVUT 1stPrize; CZ.NIC, NXP and STM Award
Master Theses
Author Title Institution Best Poster Award
Jan Říha Implementation and Effectiveness Evaluation of the VeraGreg Scheme on a Low-Cost Microcontroller FIT ČVUT
Paolo Calao Emulation-based Fault Injection of Transient Faults in Complex System-on-Chip Politecnico di Torino
Petr Socha SICAK: SIde-Channel Analysis toolKit FIT ČVUT
Enrico Rovere Automatic Generation of Functional Stress Programs with enhanced observability Politecnico di Torino 1stPrize; IEEE, CZ.NIC, NXP and STM Award
Jan Reznicek Hierarchical Dependability Models based on Non-Homogeneous Continuous Time Markov Chains FIT ČVUT 2ndPrize; ASICentrum, CZ.NIC, NXP and STM Award