PESW 2019
PESW 2019
The 7th Prague Embedded Systems Workshop
June 27-29, 2019
Roztoky u Prahy, Czech Republic
PESW 2019
The 7th Prague Embedded Systems Workshop
June 27-29, 2019
Roztoky u Prahy, Czech Republic

Keynotes

Randomness in emerging technologies: Functional robustness vs. security

Speaker: Elena-Ioana Vatajelu, TIMA - CNRS / Université Grenoble Alpes

The rapid development of low power, high density, high performance SoCs has pushed the CMOS devices to their limits and opened the field to the development of emerging technologies. The STT-MRAM and RRAM have emerged as promising choices for embedded memories due to their reduced read/write latency and high CMOS integration capability. Their inner properties make them ideal for implementation of memory blocks (mach and main memory) and, in addition, they are suitable for the implementation of basic security primitives such Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs). PUFs are emerging primitives used to implement low-cost device authentication and secure secret key generation. On the other hand, TRNGs generate random numbers from a physical process. This talk will present a survey of today’s and tomorrow’s technologies and explain how it is possible to exploit (i) the high variability affecting the electrical device characteristics to build a robust, unclonable and unpredictable PUF, and (ii) the stochastic characteristics to generate randomly distributed numbers. In addition, it will underline the conflict between functional robustness and security quality of ICs designed with such devices.

Elena-Ioana Vatajelu

Dr. Elena-Ioana Vatajelu is a researcher with CNRS in TIMA Laboratory, Grenoble, France. She has 10 years of research experience in design, test and reliability of Integrated Circuits. She received a PhD in Electronic Engineering with distinction from Universitat Politècnica de Catalunya (Spain) in 2011. She has been involved in several European Projects (FP5 and FP7) and Spanish and Italian National projects. Dr. Vatajelu has served on the Technical Program Committees and Organizing Committees of conferences and symposia in design automation and test domains, such as DATE, IEEE VTS, IEEE ETS, IEEE DCIS, IEEE DDECS. Her main research interests are on reliability and robustness assessment, design-for-reliability, test strategies and security primitives for CMOS and beyond CMOS RAMs in traditional and non-Von Neumann computing (neuromorphic and CIM) paradigms. She has published 50 journal and conference papers in the area of dependable memories.


Automotive testing challenges

Speaker: Paolo Bernardi, Politecnico di Torino, Italy

Manufacturing Automotive System-on-Chip is becoming always more challenging. That's because of the current complexity of the functionality to design, and also due to the very stringent quality requirements this kind of devices must meet. It is estimated that the quality aspects are weighting up to the 50% of the entire productive flow costs, since they "pollute" the conception of the chip with bulky test oriented circuitry and demand for several expensive test equipment to be used to ensure a perfect product being sold. The talk will depict a general scenario about all efforts to put in the manufacturing flow of a today's automotive chip, including technology qualification, design for testability, wafer sort/final test/burn-in/system level test, in-field self-test, certification tools and field return failure analysis.

Paolo Bernardi

Paolo Bernardi (MS'02 and PhD'06 in Computer Science) is an Associate Professor of the Politecnico di Torino University, where he works in the Electronic CAD and Reliability research group. His current interests includes System-on-Chip test and reliability, especially in the direction of high quality automotive devices. Prof. Bernardi is the General Chair of the Test Technology Educational Program (TTEP) and the Program Chair of the Automotive Reliability and Test (ART) Workshop held in conjunction with the International Test Conference. He was recently acting as Topic Chair for the European Test Symposium (ETS), the Design and Diagnosis of Electronic Circuits Symposium (DDECS) and the International On-Line Test Symposium (IOLTS). In 2018, he has been the General Chair of the Design and Technology of Integrated Circuits (DTIS) conference.


Hardware Acceleration Techniques for Network Monitoring and Security

Speaker: Jan Kořenek, BUT, Brno, Czech Rep.; CESNET

High-speed packet processing is important especially in network monitoring and in security systems, where any packet drop can decrease the precision of monitoring or avoid detection or mitigation of malicious traffic. Current CPUs are not able to provide enough performance for security analysis of network traffic, especially in high-speed networks. To achieve wire-speed 100 Gbps throughput every packet has to be processed in less than 5 ns. Therefore the talk will summarise time-critical operations in network security systems, which require hardware acceleration. Then It will be introduced how deep pipelines, perfect hashing, and pipelined automata can help to achieve 100 Gbps packet processing of network security systems. The talk will address also the flexibility of hardware acceleration and integration of hardware architectures into future SmartNIC devices.

Jan Kořenek

Jan Kořenek is an associate professor at Brno University of Technology. Jan has been working since 2002 on many European and national research projects, where FPGA technology was used for an acceleration of IPv6 protocol routing, network traffic monitoring, NetFlow statistic measurement and fast regular expression matching in a packet payload. These projects provide substantial experiences in the hardware acceleration of algorithms for network applications and devices. Since 2003, He worked for CESNET as a leader of Hardware group at Liberouter project. In May 2007, He co-founded INVEA-TECH company which is a university spin-off focused on high speed network monitoring and security systems. Jan is an author and co-author of many novel hardware architectures, which has been used in commercially successful devices. For example, he is an co-author of COMBO-CG 100 Gb card, which received Czech Head award in the category Industria. His research interests are in the areas of hardware acceleration, reconfigurable architectures, embedded systems and network security and monitoring. Since 2012, He has been the head of Security and Administration Tools (SAT) department at CESNET. The SAT department is focused on research and development of new tools for network infrastructure. CESNET is an association of universities of the Czech Republic and the Czech Academy of Sciences.



Keynotes

Randomness in emerging technologies: Functional robustness vs. security

Speaker: Elena-Ioana Vatajelu, TIMA - CNRS / Université Grenoble Alpes

The rapid development of low power, high density, high performance SoCs has pushed the CMOS devices to their limits and opened the field to the development of emerging technologies. The STT-MRAM and RRAM have emerged as promising choices for embedded memories due to their reduced read/write latency and high CMOS integration capability. Their inner properties make them ideal for implementation of memory blocks (mach and main memory) and, in addition, they are suitable for the implementation of basic security primitives such Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs). PUFs are emerging primitives used to implement low-cost device authentication and secure secret key generation. On the other hand, TRNGs generate random numbers from a physical process. This talk will present a survey of today’s and tomorrow’s technologies and explain how it is possible to exploit (i) the high variability affecting the electrical device characteristics to build a robust, unclonable and unpredictable PUF, and (ii) the stochastic characteristics to generate randomly distributed numbers. In addition, it will underline the conflict between functional robustness and security quality of ICs designed with such devices.

Elena-Ioana Vatajelu

Dr. Elena-Ioana Vatajelu is a researcher with CNRS in TIMA Laboratory, Grenoble, France. She has 10 years of research experience in design, test and reliability of Integrated Circuits. She received a PhD in Electronic Engineering with distinction from Universitat Politècnica de Catalunya (Spain) in 2011. She has been involved in several European Projects (FP5 and FP7) and Spanish and Italian National projects. Dr. Vatajelu has served on the Technical Program Committees and Organizing Committees of conferences and symposia in design automation and test domains, such as DATE, IEEE VTS, IEEE ETS, IEEE DCIS, IEEE DDECS. Her main research interests are on reliability and robustness assessment, design-for-reliability, test strategies and security primitives for CMOS and beyond CMOS RAMs in traditional and non-Von Neumann computing (neuromorphic and CIM) paradigms. She has published 50 journal and conference papers in the area of dependable memories.


Automotive testing challenges

Speaker: Paolo Bernardi, Politecnico di Torino, Italy

Manufacturing Automotive System-on-Chip is becoming always more challenging. That's because of the current complexity of the functionality to design, and also due to the very stringent quality requirements this kind of devices must meet. It is estimated that the quality aspects are weighting up to the 50% of the entire productive flow costs, since they "pollute" the conception of the chip with bulky test oriented circuitry and demand for several expensive test equipment to be used to ensure a perfect product being sold. The talk will depict a general scenario about all efforts to put in the manufacturing flow of a today's automotive chip, including technology qualification, design for testability, wafer sort/final test/burn-in/system level test, in-field self-test, certification tools and field return failure analysis.

Paolo Bernardi

Paolo Bernardi (MS'02 and PhD'06 in Computer Science) is an Associate Professor of the Politecnico di Torino University, where he works in the Electronic CAD and Reliability research group. His current interests includes System-on-Chip test and reliability, especially in the direction of high quality automotive devices. Prof. Bernardi is the General Chair of the Test Technology Educational Program (TTEP) and the Program Chair of the Automotive Reliability and Test (ART) Workshop held in conjunction with the International Test Conference. He was recently acting as Topic Chair for the European Test Symposium (ETS), the Design and Diagnosis of Electronic Circuits Symposium (DDECS) and the International On-Line Test Symposium (IOLTS). In 2018, he has been the General Chair of the Design and Technology of Integrated Circuits (DTIS) conference.


Hardware Acceleration Techniques for Network Monitoring and Security

Speaker: Jan Kořenek, BUT, Brno, Czech Rep.; CESNET

High-speed packet processing is important especially in network monitoring and in security systems, where any packet drop can decrease the precision of monitoring or avoid detection or mitigation of malicious traffic. Current CPUs are not able to provide enough performance for security analysis of network traffic, especially in high-speed networks. To achieve wire-speed 100 Gbps throughput every packet has to be processed in less than 5 ns. Therefore the talk will summarise time-critical operations in network security systems, which require hardware acceleration. Then It will be introduced how deep pipelines, perfect hashing, and pipelined automata can help to achieve 100 Gbps packet processing of network security systems. The talk will address also the flexibility of hardware acceleration and integration of hardware architectures into future SmartNIC devices.

Jan Kořenek

Jan Kořenek is an associate professor at Brno University of Technology. Jan has been working since 2002 on many European and national research projects, where FPGA technology was used for an acceleration of IPv6 protocol routing, network traffic monitoring, NetFlow statistic measurement and fast regular expression matching in a packet payload. These projects provide substantial experiences in the hardware acceleration of algorithms for network applications and devices. Since 2003, He worked for CESNET as a leader of Hardware group at Liberouter project. In May 2007, He co-founded INVEA-TECH company which is a university spin-off focused on high speed network monitoring and security systems. Jan is an author and co-author of many novel hardware architectures, which has been used in commercially successful devices. For example, he is an co-author of COMBO-CG 100 Gb card, which received Czech Head award in the category Industria. His research interests are in the areas of hardware acceleration, reconfigurable architectures, embedded systems and network security and monitoring. Since 2012, He has been the head of Security and Administration Tools (SAT) department at CESNET. The SAT department is focused on research and development of new tools for network infrastructure. CESNET is an association of universities of the Czech Republic and the Czech Academy of Sciences.