PESW 2016
The 4th Prague Embedded Systems Workshop
June 30 - July 2, 2016
Roztoky u Prahy, Czech Republic

Preliminary Program

Thursday, June 30 9:00 - 10:00 Registration
10:00 Opening
10:00 - 12:00 Session 1 - FPGA and logic design
Development of a sound recording system for audio cassette duplication on an industrial scale (Dominika Pichlová and Matěj Bartík)
P4-to-FPGA: Translating P4 to VHDL (Pavel Benáček and Hana Kubátová)
Emulator of Contactless Chip Cards in FPGA (Stanislav Jeřábek)
Utilization of XOR gates in logic synthesis (Ivo Háleček, Petr Fišer, Jan Schmidt)
12:00 - 13:15 Lunch
13:15 - 14:00 Keynote: High Level and Energy Efficient Hardware/Software Co-Design of Heterogeneous Systems (Martin Margala)
14:00 - 16:00 Session 2 - Fault tolerance
Software-implemented Fault-Tolerant Program Generation (Ondřej Čekan and Zdeněk Kotásek)
Fault Tolerant Field Programmable Neural Networks (Martin Krčma and Zdeněk Kotásek)
A Systematic Approach to the Description of Fault-tolerant Systems (Jakub Lojda and Zdeněk Kotásek)
Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems (Karel Szurman, Lukáš Mičulka and Zdeněk Kotásek)
16:30 - 23:00 Social Event, Dinner
Friday, July 1 9:30 - 10:30 Session 3 - Real-time systems
Fault-tolerant Multicore Real-time Scheduling (Stefan Krämer, Stanislav Racek and Juergen Mottok)
Real Time Isolated Word Recognition using a GPP vs. DSP (Gabi Shafat and Dor-Ezra Mizrahi)
10:30 - 11:00 Coffee break
11:00 - 13:00 Session 4 - Testing & verification, security
A new algorithm for embedded memories division for MBIST testing in SoCs (Juraj Šubín and Elena Gramatová)
Self-Test and Self-Repair Principles Applied to Hamming Encoders (Davide Dicorato and Heinrich Theodor Vierhaus)
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems (Jakub Podivínský and Zdeněk Kotásek)
Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis (Vojtěch Miškovský, Hana Kubátová and Martin Novotný)
13:00 - 14:00 Lunch
14:00 - 15:00 Keynote: How We Verified SoC Chip (Robert Kvaček - ASICentrum)
15:00 - 16:30 Coffee break & student posters
16:30 - 18:00 Session 5 - Networks
Future plans for bulk configuration and visualization of NETCONF devices (David Alexa)
Detecting Spoofed Time in NTP Traffic (Tomáš Čejka and Alejandro Robledo)
Overload-resistant Network Traffic Analysis (Marek Švepeš and Tomáš Čejka)
18:00 Closing
Saturday, July 2 Sightseeing tour