Keynotes

High Level and Energy Efficient Hardware/Software Co-Design of Heterogeneous Systems

Speaker: Martin Margala, FEL CTU

Energy efficient computation is becoming a main focus for computing systems design. It has become a necessity to consider power aspects when dealing with large scale datacentric and high performance applications. Designing a large computing center can now require access to natural free cooling and cheap electricity in order to be economically viable. It is forecasted that this trend will continue and will reach a critical point when we transition to exascale computing i.e. systems capable of performing 10exp18 operations per second, a thousand fold increase relative to the current petascale capabilities. A significant change in the way we do computation is required in order to support such an increase in performance. This change among other things will have to come from using more efficient computing devices as measured by performance per watt. It has been shown, both theoretically and in practice, that using heterogeneous systems i.e. systems using different types of computing devices can be more power efficient then homogenous computing systems. One of the main challenges in using heterogeneous systems is the difficulties in programming and maintaining systems with different types of computing devices, programming languages, development tools etc. This work is an attempt at furthering our knowledge of designing and programming power efficient heterogeneous systems using programming languages and frameworks that operate at abstract and hardware agnostic levels.

Martin Margala, Ph.D.
Fulbright Distinguished Chair in EE
Chair and Professor
Electrical and Computer Engineering Department
301 Ball Hall
University of Massachusetts Lowell
One University Avenue
Lowell, MA 01854

Presently at:
Department of Microelectronics
Room 219
Faculty of Electrical Engineering
Czech Technical University
Technicka Street 2
Prague 6 Dejvice
Czech Republic

How We Verified SoC Chip

Speaker: Robert Kva�ek, ASICentrum

The logic verification of SoC device is not just a construction of simple logic testbench and set of testcases. The sufficient coverage and thus bug risk mitigation requires system approach and several different verification methods combined together. The presentation shows an example of Bluetooth Low Energy SoC device logic and system verification (UVM logic testbench, gate-level simulation, mixed-mode simulation, FPGA, even analog simulation). UVM testbench with the device top-level as DUV was used. The logic tightly linked to analog blocks was simulated in mixed-mode environment. Embedded SW was developed as a part of the device, so methodology of SW verification is described as well. A specific problem of logic working at very low voltage and trap caused by using standard verification method will be mentioned. As the final part, verification of production test patterns is described.