Keynotes

Approximate computing in neural networks

Speaker: Vojtěch Mrázek, Brno University of Technology, Faculty of Information Technology, Czech Rep.

Neural networks and their accelerators appear in many embedded applications that are power constrained. One way to reduce the power consumption of these networks without significantly changing the architecture is to exploit the benefits of approximate computing. This approach exploits the fact that users are willing to accept some error at the cost of lower energy consumption. In this keynote, approaches for the controlled introduction of error into the computational path will be presented. It will be demonstrated approaches for an error-resilience evaluation and for an efficient mapping of layers to approximation components.

Resilient RISC-V processor for aerospace applications: from on-chip sensors to AI-based reliability prediction

Speaker: Fabian Vargas, IHP - Leibniz Institute for High Performance Microelectronics, Germany

Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced integrated circuit (IC) and electronics since the sixties. Nevertheless, it is well recognized that such scaling has introduced new (and major) reliability challenges to the semiconductor industry.
This talk describes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging during IC lifetime, and ultimately predicting in-flight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in real-time operating system (RTOS) is further introduced.
Currently, this on-chip infrastructure is being implemented by IHP in different versions of a quad-core RISC-V processor. This IC has been designed by using a CMOS 130nm rad-hard technology also developed at IHP. An FPGA-mapped demonstrator of the developed RISC-V processor and experimental results will be presented and discussed.

Industrial talks

Comprehensible multi-modal detection of cyber threats

Speaker: Martin Kopp, CISCO

Detection of malicious activities is a very complex task and much effort has been invested into research of its automation. However, vast majority of existing methods operate only in a narrow scope which limits them to capture only fragments of the evidence of malware’s presence. Consequently, such approach is not aligned with the way how the cyber threats are studied and described by domain experts. In this talk, we discuss these limitations and design a detection framework which combines observed events from different sources of data. Thanks to this, it provides full insight into the attack life cycle and enables detection of threats that require this coupling of observations from different telemetries to identify the full scope of the incident. We demonstrate applicability of the framework on a case study of a real malware infection observed in a corporate network.

Risk-based access control system

Speaker: Tomáš Trpišovský, IMA s.r.o., Czech Rep.

Traditional (physical) access control systems are well-established mechanisms, allowing organizations to determine who should be able to access which physical space. During the Covid-19 pandemic, additional features to the reduce the risks of individuals when entering spaces became popular or even mandatory. We refer to this as risk-based access control (RiBAC). For instance, automatic scanning for protective wear (e.g., whether an individual wears a mask), body temperature checks or digital health certificates, certifying that one has been negatively tested for, or vaccinated against, Covid-19.
In this context, we discuss the use of privacy-preserving cryptography in order to be able to have privacy-preserving risk-based access control systems in place for any potential future pandemic.

Economically self-sufficient education of software development

Speaker: Tomáš Martinec, Institute for Support of Innovative Education, Czech Republic

The talk briefly introduces activities of the Institute and then presents outcomes of its internal project of innovating software development education for high-school level students. The students engage in real-world software development tasks with support of mentors or their peers. This way they develop their software development skills in a very fast manner, many times even able to develop enough code of value that it covers almost wholly the expenses of this approach to education.

Enhancing connectivity with I3C

Speaker: Adam Berlinger, STMicroelectronics, Czech Rep.

I3C is a serial communication interface developed by the MIPI® Alliance that aims to improve and overcome limitations of the well-established I2C. It allows achieving higher data rates, improving power efficiency and reducing signal count. Since the standard is developed by the MIPI® Alliance and is partially open, we might see broader adoption in near future.
This presentation gives a brief overview on how the I3C bus works, how it is compatible with I2C and what are its main advantages. We will have a look on different transfers occurring on the bus as well as some advanced features.

Is a Matter future of Smart homes?

Speaker: Jiří Vlček, STMicroelectronics, Czech Rep.

The goal of the Matter project is to simplify development for manufacturers and increase compatibility for consumers with a unified connectivity protocol. Matter is an application layer protocol using existing technologies such as Thread, Wifi, Ethernet and BLE. The main idea of the Matter is to have only one Gateway and one Smart phone app at home to control all the devices around - no matter who is vendor of the device. By building upon Internet Protocol (IP), the project aims to enable communication across smart home devices, mobile apps, and cloud services and to define a specific set of IP-based networking technologies for device certification.